1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly to a multi-port random access memory (hereinafter as "multi-port RAM").
2. Description of the Background Art
FIG. 11 is a schematic block diagram of the configuration of a conventional 2-port static random access memory 6000 (hereinafter as "2-port SRAM").
FIG. 11 shows the configuration of 2-port SRAM 6000 having memory cells corresponding to 4 bits in a matrix of two rows and two columns for ease of illustration.
Referring to FIG. 11, 2-port SRAM 6000 includes a memory cell array 10 having memory cells DM1 to DM4 for 4 bits arranged in a matrix of 2 rows and 2 columns, read word lines RWL0 to RWL1 provided corresponding to the rows of memory cells to select a row in memory cell array 10 at the time of reading data, write word lines WWL0 to WWL1 provided corresponding to the rows of memory cells to select a row in memory cell array 10 at the time of writing data, read bit lines RB0, /RB0 provided in common to memory cells DM1 and DM3 to read out data from these memory cells, read bit lines RB1, /RB1 provided in common to memory cells DM2 and DM4 to read out data from these memory cells, write bit lines WB0, /WB0 provided in common to memory cells DM1 and DM 3 to write data to these memory cells, write bit lines WB1, /WB1 provided in common to memory cells DM2 and DM4 to write data to these memory cells, and a precharge circuit 1 to charge read bit lines RB0, /RB0, RB1, and /RB1.
Two-port SRAM 6000 is externally provided with a read clock signal RCLK and a read address signal RA0, RA1 and read data RD is output in response to these signals. More specifically, a read address decode circuit 3 receives read clock signal RCLK and a read address signal RA0, RA1, selects read word line RWL0 or RWL1 and outputs a read column select signal RY0, RY1 to select a read bit line and a precharge signal /PCG to control precharge circuit 1. A reading circuit 5 amplifies the potential of a read bit line and outputs read data RD.
Meanwhile, 2-port SRAM 6000 is externally provided with a write clock signal WCLK and a write address signal WA0, WA1 and write data WD is stored in response to these signals. More specifically, a write address decode circuit 4 receives write clock signal WCLK and a write address signal WA0, WA1, selects word line WWL0 or WWL1 and outputs a write column select signal WY0, WY1 to select a write bit line. A writing circuit 6 writes write data WD to a selected memory cell through the write bit line.
FIG. 12 is a circuit diagram showing the configuration of memory cell DM1 shown in FIG. 11. Note that the other memory cells DM2 to DM4 basically have the same configuration as memory cell DM1 except that word lines or bit lines to be connected therewith are different.
Referring to FIG. 12, memory cell DM1 includes a latch circuit including a P-channel transistor P1 and an N-channel transistor N1 connected in series between a power supply potential Vcc and a ground potential GND and a P-channel transistor P2 and an N-channel transistor N2 connected in series between power supply potential Vcc and ground potential GND. The gates of transistors P1 and N1 are connected together to the connection node /SN (hereinafter as "storage node /SN") of transistors P2 and N2, while the gates of transistors P2 and N2 are connected together to the connection node SN (hereinafter as "storage node SN") of transistors P1 and N1. More specifically, P-channel transistors P1 and P2 operate as load transistors and N-channel transistors Ni and N2 operate as driver transistors.
An N-type read access transistor N3 is provided between read bit line RB0 and storage node SN, an N-type read access transistor N4 is provided between read bit line /RB0 and storage node /SN, and the gate potentials of transistors N3 and N4 are controlled by read word line RWL0.
N-channel transistors N5 and N6 are connected in series between storage node SN and ground potential GND, while N-channel transistors N7 and N8 are connected in series between storage node /SN and ground potential GND. The gate potentials of N-channel transistors N5 and N7 (hereinafter as "write access transistors") are controlled by write word line WWL0, and the gates of N-channel transistors N6 and N8 are connected to write bit lines /WB0 and WB0, respectively.
FIG. 13 is a timing chart for use in illustration of the operation of the conventional 2-port SRAM 6000 described in conjunction with FIGS. 11 and 12.
In FIG. 13, both a read access and a write access are made to the same memory cell row such as a memory cell row to which memory cells DM1 and DM2 belong.
In an initial state, read bit lines RB0, /RB0 are both precharged to power supply potential Vcc.
At time T0, the potential level of read word line RWL0 rises, and a read access operation to memory cell DM1 is started. The potential of one of the read bit lines, here the potential of read bit line RB0 falls, which generates a potential difference between read bit lines RB0 and /RB0. Meanwhile, regarding memory cell DM2, in response to read word line RWL0 attaining an "H" level, the potential of read bit line RB1 falls, which generates a potential difference between read bit lines RB1 and /RB1.
Then, at time T1, the potential level of write word line WWL0 rises, and a write access operation to memory cell DM2 is started. Here, writing circuit 6 treats the potential level of write bit line WB1 among write bit lines WB1 and /WB1 as an "H" level (power supply potential level) based on write data WD and writes the "H" level to the memory cell. In this case, in response to write word line WWL0 attaining an "H" level, transistors N5 and N7 in memory cell DM2 are in a conductive state. As a result, transistor N8 in memory cell DM2 conducts in response to the "H" level potential of write bit line WB1, and tries to lower the potential of the storage node /SN in memory cell DM2. However, since read word line RWL0 has attained an "H" level, read access transistor N4 in memory cell DM2 is in a conductive state. Therefore, read bit line /RB1 must be also discharged by write access transistors N7 and N8.
Meanwhile, on the side of storage node SN in memory cell DM2, access transistor N3 is in a conductive state, and therefore load transistor P1 in memory cell DM2 must charge not only storage node SN but also read bit line RB1.
Efforts are generally made to reduce the area occupied by transistors in a memory cell in order to achieve high density integration, and the transistor size is also small in SRAM 6000, and therefore the current driving capability is not large. In addition, a number of memory cells are typically connected to a read bit line, and the line capacitance is large. As a result, it takes very long between time T1 when a writing operation to memory cell DM2 is started and time T2 the potential difference between read bit lines RB1 and RB1 is inverted. P-channel transistors P1 and P2 in particular are not only small in size but also have current driving capability about half that of an N-channel transistor having the same size, and therefore the necessity of charging a read bit line with a load transistor is a great obstacle to reduction in access time.